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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 ? semiconductor msm80c48/49/50 msm80c35/39/40 cmos 8-bit microcontroller general description the oki msm80c48/msm80c49/msm80c50 are 8-bit, low-power, high-performance micro- controllers implemented in silicon-gate complementary metal-oxide semiconductor technology. integrated within these chips are 8k/16k/32k bits of mask program rom, 512/1024/2048 bits of data ram, 27 i/o lines, built-in 8 bit timer/counter, and oscillator. program memory and data paths are byte wide. eleven new instructions have been added to the nmos version's instruction set, thereby optimizing power down, port data transfer, decrement and port float functions. available in 40-pin plastic dip (rs) or 44-pin plastic flat packages qfp (gsk). features ? lower power consumption enabled by cmos silicon gate process ? completely static operation ? improved power-down feature ? instruction cycle : 1.36 m s (11 mhz) v cc =4.5 to 6.0 v (msm80c48/49) 2.5 m s (6 mhz) v cc =3.5 to 6.0 v (msm80c50) ? 111 instructions ? all instructions are usable even during execution of external rom instructions. ? operation facility addition, logical operations, and decimal adjust ? program memory (rom) : 1k words 8 bits (msm80c48) : 2k words 8 bits (msm80c49) : 4k words 8 bits (msm80c50) ? data memory (ram) : 64 words 8 bits (msm80c48) : 128 words 8 bits (msm80c49) : 256 words 8 bits (msm80c50) ? two sets of working registers ? external and timer interrupts ? two test inputs ? built-in 8-bit timer counter ? extendable external memory and i/o ports ? i/o port input-output port : 2 ports 8 bits data bus input-output port : 1 port 8 bits ? single-step execution function ? wide range of operating voltage, from + 2.5 v to + 6 v of v cc ? high noise margin action ? compatible with intel's 8048, 8049 and 8050 ? package 40-pin plastic dip (dip40-p-600-2.54) : (msm80c48- rs) (msm80c49- rs) (msm80c50- rs) (msm80c35rs) (msm80c39rs) (msm80c40rs) 44-pin plastic qfp(qfp44-p-910-0.80-2k) : (msm80c48- gs-2k) (msm80c49- gs-2k) (msm80c50- gs-2k) (msm80c35gs-2k) (msm80c39gs-2k) (msm80c40gs-2k) indicates the code number. e2e1022-27-y4 this version: jan. 1998 previous version: nov. 1996
2/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 block diagram 8 8 pla bus buffer port1 bus buffer and latch bus latch and low pc temp register instruc- tion register multiplexer register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 8-level stack optional second register bank data store decoder data memory (ram) 64 8 bits msm80c48rs 128 8 bits msm80c49rs 256 8 bits msm80c50rs ram address register test0 test1 int flag0 flag1 timer flag carry acc acc bit test condi- tional branch logic lower program counter (8) timer/event counter (8) program memory (rom) 1k 8bits msm80c48rs 2k 8bits msm80c49rs 4k 8bits msm80c50rs 2 or 3 higher program counter (4) ?4 80 port2 latch (high4) port2 latch (low4) and expander port i/o test1 port2 bus buffer 8 (port 2) 44 4 8 (8) accumulator (8) accumulator latch (8) temp reg (8) flags arithmetic logic unit (8) decimal adjust wr rd ss psen ale xtal2 xtal1 ea prog reset int interrupt initialize prom/ expander strobe cpu memory separate oscillator xtal address latch, data latch strobe cycle clock program memory enable single step read strobe write strobe control and timing osc freq (data bus port) (port 1)
3/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 pin configuration (top view) 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v ss t0 xtal1 xtal2 reset ss int ea rd psen wr ale db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 p2 0 v cc t1 p2 7 p2 6 p2 5 p2 4 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 v dd prog p2 3 p2 2 p2 1 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 v dd p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 nc p1 6 p1 7 p2 4 db 3 db 2 db 1 db 0 ale wr psen rd ea int ss 44 43 42 41 40 39 38 37 36 35 34 nc prog p2 3 p2 2 p2 1 p2 0 v ss db 7 db 6 db 5 db 4 12 13 14 15 16 17 18 19 20 21 22 nc p2 5 p2 6 p2 7 t1 v cc t0 xtal1 xtal2 nc reset nc: no-connection pin 40-pin plastic dip 44-pin plastic qfp
4/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 pin descriptions symbol type description p1 0 -p1 7 (port 1) 8-bit quasi-bidirectional port i/o p2 0 -p2 7 (port 2) 8-bit quasi-bidirectional port the high-order four bits of external program memory addresses can be output from p2.0-p2.3, to which the i/o expander msm82c43rs may also be connected. i/o db 0 -db 7 (bus) bidirectional port the low-order eight bits of external program memory address can be output from this port, and the addressed instruction is fetched under the control of psen signal. also, the external data memory address is output, and data is read and written synchronously using rd and wr signals. the port can also serve as either a statically latched output port or a non-latching input port. i/o t0 (test 0) the input can be tested with the conditional jump instructions jt0 and jnt0. the execution of the ent0 clk instruction causes a clock output. i/o t1 (test 1) the input can be tested with the conditional jump instructions jt1 and jnt1. the execution of a strt cnt instruction causes an internal counter input. i int (interrupt) interrupt input. if interrupt is enabled, int input initiates an interrupt. interrupt is disabled after a reset. also testable with a jni instruction. can be used to terminate the power-down mode. (active "0" level) i rd (read) a signal to read data from external data memory. (active "0" level) o wr (write) a signal to write data to external data memory. (active "0" level) o ale address & data latch clock this signal is generated in each cycle. it may be used as a clock output. external data memory or external program memory is addressed upon the falling edge. for the external rom, this signal is used to latch the bus port data upon the ale signal rise-up after the execution of the outl bus, a instruction. o psen program store enable a signal to fetch an instruction from external program memory (active "0" level) o reset reset input initialize the processor. (active "0" level) used to terminate the power-down mode. i ss (single step) a program is executed step by step. this pin can also be used to control internal oscillation when the power-down mode is reset. (active "0" level) i ea (external access) when held at high level, all instructions are fetched from external memory. (active "1" level) i prog (expander strobe) this output strobes the msm82c43rs i/o expander. o
5/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 pin descriptions (continued) note: a minimum of two machine cycles are required in reset pulse duration under the specified power supply and stable oscillator frequency. symbol type description xtal1 (crystal 1) one side of the internal crystal oscillator. an external clock can also be input. i xtal2 (crystal 2) other side of the internal crystal oscillator. o v cc power supply pin v dd standby control input. normally, "1" level. when set to "0" level, oscillation is stopped and prosessor goes into standby mode. v ss gnd
6/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ta=25c C0.5 to 7 v input voltage v i ta=25c C0.3 to v cc +0.5 v storage temperature t stg C65 to +150 c recommended operating conditions parameter symbol condition range unit supply voltage v cc f osc =dc to 11mhz* +2.5 to +6 v ambient temperature t a C40 to +85 c fan out n mos load 10 ttl load 1 * minimum operating voltage is dependent on frequency.
7/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 msm80c48/49/50 guaranteed operating range 1.5mhz 6mhz 11mhz guaranteed operating range msm80c40/80c50 6 45 3 2 1 10 100 ta=C40 to +85c ( m sec) cycle time (t cy ) supply voltage (v cc ) (v) msm80c35/80c48/80c39/80c49
8/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 electrical characteristics dc characteristics parameter symbol condition typ. min. max. unit mea- suring circuit "l" input voltage v il C0.5 0.13 v cc v "h" input voltage *1 v ih 0.4 v cc v cc v "h" input voltage *2 v ih 0.7 v cc v cc v "l" output voltage *3 v ol i ol =2 ma 0.45 v "l" output voltage *4 v ol i ol =1.6 ma 0.45 v 1 "h" output voltage *3 v oh i oh =C400 m a 0.75 v cc v "h" output voltage *4 v oh i oh =C50 m a 0.75 v cc v "h" output voltage *3 v oh i oh =C20 m a 0.93 v cc v "h" output voltage *4 v oh i oh =C10 m a 0.93 v cc v input leakage curent i il v ss v in v cc 5 m a2 output leakage current *5 i ol v ss v o v cc 5 m a3 reset input current i r v in =0.7 v cc C20 C50 C80 m a v in =0.13 v cc C3 C8 C15 m a 2 ss input current *6 i ss pull-up (v in =v il ) 205080 m a pull-down (v in =v ih ) C6 C15 C25 m a p1, p2 input current i p1 , i p2 v in =v ih C300 C600 C900 m a 2 v in =v il C10 C40 C80 m a at hardware power down *7 ta=25c, v cc =2.0 v 10 power down mode standby current i ccs at hlts execution *7 ta=25c, v cc =2.0 v 10 m a v cc =4 v, f=1 mhz 0.5 v cc =4 v, f=6 mhz 1.0 v cc =4 v, f=11 mhz 2.0 v cc =5 v, f=1 mhz 1.0 power supply current (halt mode) i cc v cc =5 v, f=6 mhz 2.0 ma v cc =5 v, f=11 mhz 3.0 v cc =6 v, f=1 mhz 1.5 v cc =6 v, f=6 mhz 3.0 4 v cc =6 v, f=11 mhz 5.0 v cc =4 v, f=1 mhz 1.5 v cc =4 v, f=6 mhz 5.0 v cc =4 v, f=11 mhz 10 v cc =5 v, f=1 mhz 2.5 power supply current i cc v cc =5 v, f=6 mhz 7.5 ma v cc =5 v, f=11 mhz 15 v cc =6 v, f=1 mhz 5.0 v cc =6 v, f=6 mhz 10 v cc =6 v, f=11 mhz 20 (v cc =5 v10%, ta=C40 to +85c)
9/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 *1 this does not apply to reset, xtal1, xtal2, v dd , and ea. *2 reset, xtal1, xtal2, v dd , and ea. *3 bus, rd , wr , psen , ale, prog *4 other outputs *5 high-impedance state *6 this operates as a pull-down resistor when the oscillation is stopped in the hlts or v dd power-down mode and as a pull-up resistor in other states. *7 this does not contain flow out current from i/o ports and signal pins.
10/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 ac characteristics parameter symbol v cc =5 v10% 11 mhz clock variable clock 0 to 11 mhz unit min. max. min. max. ale pulse width t ll 150 3.5tC170 ns address setup time (up to ale) t al 70 2tC110 ns address hold time (from ale) t la 50 tC40 ns bus port latch data setup time (up to ale rising edge) t bl 110 2.5t C115 ns bus port latch data hold time (from ale rising edge) t lb 90 1.5 tC45 ns control pulse width ( rd , wr ) t cc1 480 7tC155 ns data setup time (before wr ) t dw 390 6tC155 ns data hold after time (after wr ) t wd 40 2tC140 ns data hold time (after rd , psen ) t dr 0 110 0 1.5tC30 ns psen to data-in t rd2 190 5tC265 ns address setup to wr t aw 300 6tC245 ns address setup to data-in t ad1 730 12tC360 ns address float to psen t afc2 10 10 ns prog to input data valid t pr 650 9tC170 ns input data hold time t pf 0 140 0 1.5t ns output data setup time t dp 250 6tC290 ns output data hold time t pd 40 3tC230 ns prog pulse width t pp 700 10tC210 ns port 2 i/o setup time t pl 160 4.5C250 ns port 2 i/o hold time t lp 15 1.5tC120 ns (v cc =2.5v to 6v (*1), ta=C40 to +85c) control pulse width ( psen ) t cc2 350 6tC200 ns rd to data-in t rd1 350 5tC265 ns address setup to instruction t ad2 460 8tC265 ns address float to rd , wr t afc1 140 2tC40 ns port control setup time (up to prog falling edge) t cp 50 2tC130 ns control pulse setup time from ale ( psen ) t lafc2 60 tC30 ns control pulse setup time from ale ( rd , wr ) t lafc1 200 3tC75 ns control pulse up to ale ( rd , wr , prog ) t ca1 50 1.5tC85 ns control pulse up to ale ( psen ) t ca2 320 4.5tC90 ns port control hold time (from prog falling edge) t pc 100 4tC260 ns port output data (from ale) t pv 510 4t+145 ns t0 cycle t oprr 270 3t ns instruction execution time t cy 1.36 15t m s note : control output : c l =80pf bus output : c l =150pf [for 20 pf (t al , t afc1 , t afc2 )] *1 minimum operating voltage is dependent on frequency.
11/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 measuring circuits v cc gnd inputs output v ih v il (*2) v a (*3) i o 1 v cc gnd inputs output (*1) 2 v cc gnd inputs output v ih v il a (*3) 3 v cc gnd inputs output v ih v il a (*3) 4 a v cc gnd inputs output v ih v il (*2) (*3) 5 t xxx t xxx v ol v oh v ol v oh v ih v il cl i o o *1 this is repeated for each specified input pin. *2 this is repeated for each specified output pin. *3 input logic for setting the specified state
12/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 timing diagram instruction fetch (from external program memory) read (from external data memory) t cy t ll t afc t cc t al t la t rd t dr t bl t lb t ad latch data floating instruction latch data address address ale psen bus address t cc t ad t afc t rd t dr float- ing data float- ing address ale rd bus
13/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 write (to external memory) low-order 4 bits input/output of port 2 when expanded i/o port is used (in external program memory access mode) t cc t aw t dw float- ing data address t wd ale bus wr address pch t pl t lp t dp t pd t pr t pf t cp t pc t pp port data port control output data pch port data port control input data ale prog p2 0-3 (output mode) p2 0-3 (input mode)
14/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 functional description added functions of msm80c48, msm80c49 and msm80c50 the msm80c48, msm80c49 and msm80c50 are basically incorporated with the capabilities of intel's 8048, 8049, and 8050 plus the following new functions: 1. power-down mode enhancements 1.1 power-down by software (1) clock (see item 4, "power-down mode", for details.) a. crystal oscillator halt (hlts instruction) power requirements can be minimized. b. clock supply halt (halt instruction) restart is accomplished without oscillator wait. (2) i/o ports i/o port floating instructions power consumption resulting from inputs/outputs can be minimized with flt and fltt instructions. port floating is cancelled by executing fres instruction, "0" level at int pin or "0" level at reset pin. (3) six types of power-down can be done by a combination of hlts/halt and flt/fltt instructions. 1.2 power-down by hardware (see 4.3, power-down mode by v dd pin utilization for details.) crystal oscillators can be halted by controlling the v dd pin, thereby floating all i/o ports for minimum power consumption. 2. additional instructions (11) hlts mov a, p2 halt movp1, @ r3 flt movp1 p, @r3 fltt dec @rr fres djnz @ rr, addr mov a, p1 3. improved uses of bus p 0 - 7 , p1 0 - 7 , p2 0 - 7 , and ss pins 3.1 bus p 0 - 7 the msm80c48, msm80c49, and msm80c50 remove the limitation on the use of outl bus, a instructions during the external rom access mode by having an independent data latch and external rom mode address latch in bus p 0 - 7 . consequently, there is no need to relocate bus port instructions when in the external rom access mode. 3.2 p 10 - 7 and p2 0 - 7 the msm80c48, msm80c49 and msm 80c50 are designed to minimize power consumption when p1 0 - 7 and p2 0 - 7 are used as input/output ports, to maximize the performance of cmos. when these ports are used as output ports, the acceleration circuit is actuated only when
15/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 output data changes from "0" to "1", thus speeding up the rise time of the output signals. when these ports are used as input ports, the internal pull-up resistor becomes approximately 9 k w when input data is "1". the internal pull-up resistor rises to approximately 100 k w when input data is "0". thus, a high noise margin can be obtained by selecting the impedance and thus the outflow of current is minimized whenever these ports are used as output or input ports. 3.3 clock generation control via the ss pin when the crystal oscillator is halted in the hlts or hardware power-down mode, the ss pin is pulled down by a resistor of 20 to 50 k w , while its internal pull-up resistor of 200 to 500k w is isolated from v cc . when the power-down mode is cancelled, the internal resistor of the ss pin is changed from pull-down to pull-up. consequently, the cpu can be halted for any period of time until the crystal oscillator resumes normal oscillation when a capacitor is connected to the ss pin. 4. power-down mode the msm80c48, msm80c49, and msm80c50 power-down mode can be enabled in two different ways through software by a combination of clock control and port floating instructions, and through hardware by control of the v dd pin. 4.1 software power-down mode power-down mode can be done by a combination of the following instructions. (1) halt (clock supply halt to control circuit) instruction code : description : although crystal oscillator operation is continued, the clock supply to the cpu control circuit is halted and cpu operations are suspended. when cancelling this software mode, restart is accomplished without oscillator wait. (2) hlts (oscillation stop) instruction code : description : the oscillator operation is halted and cpu operations are suspended. in cancelling this power down mode, connecting a capacitor to the ss pin enables a reasonable wait period to be accomplished before normal operation is resumed. [except in the case of using the reset pin] (3) flt (floating p1 0 - 7 , p2 0 - 7 , and bp 0 - 7 ) instruction code : description : 00000001 10000010 10100010 p1 p2 bp internal rom mode floating floating floating external rom mode floating p2 0 - 3 operation operation
16/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 details of ic pin status as a result of executing the flt instruction are shown in the above table. (4) fltt (floating of all output pins) instruction code : description : details of ic pin status as a result of executing the fltt instruction are shown in above table. example 1 : power-down mode accomplished by stopping oscillation. m can be set by execution of hlts [82h] instruction. example 2 : power-down mode accomplished by stopping the clock supply to the cpu control circuit. m can be set by execution of halt [01h] instruction. example 3 : power-down mode by floating of p1 0 - 7 , p2 0 - 7 and bp 0 - 7 , and subsequent stopping of cpu oscillation. m can be set by first executing the flt [a2h] instruction, followed by the hlts [82h] instruction. example 4 : power-down mode by floating p1 0 - 7 , p2 0 - 7 and bp 0 - 7 , and then stopping the clock supply to the cpu control circuit. m can be set by first executing the flt [a2h] instruction, and then the halt [01h] instruction. example 5 : power-down mode by floating all output pins, followed by stopping oscillation. m can be set by first executing the fltt [c2h] instruction followed by execution of the hlts [82h] instruction. example 6 : power-down mode by floating all output pins, followed by stopping of the clock supply to the cpu control circuit. m can be set by first executing the fltt [c2h] instruction, followed by execution of the halt [01h] instruction. connect the pull-up resistor or pull-down resistor to port pin and fix the output port pin level to either 1or 0 when output port is set to floating. 11000010 ale p2 xtal internal rom mode floating floating operation external rom mode operation p2 0 - 3 operation operation psen floating operation prog floating floating wr floating floating pd floating floating t0 out floating floating p1 floating floating bp floating operation
17/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 4.2 cancellation of software power-down mode the power-down mode status outlined above in examples 1 to 6 can be cancelled by using either the interrupt pin or the reset pin. (1) use of the int pin during external interrupt enable mode (i.e. following execution of en i instruction). m the clock generator is activated and the cpu is started up when a "0" level is applied to the int pin. if this "0" level is maintained until the occurrence of at least 2 ale output signals, an external interrupt is generated, and execution proceeds from address 3. if, however, the power-down is entered during the interrupt processing routine, execution resumes just after the power-down instruction. (2) use of the int pin during external interrupt disable mode (i.e. following execution of dis i instruction or hardware reset) m the clock generator is activated and the cpu is started up when a "0" level is applied to the int pin. when "0" level is maintained until the occurrence of at least 2 ale output signals, execution is resumed just after the power-down instruction. (3) use of the reset pin m the clock generator is activated and the cpu started up when a "0" level is applied to the reset pin. if this "0" level is maintained until the occurrence of at least 2 ale output signals, the cpu is reset and execution proceeds from address 0. in case cancellation is done in oscillation stop mode, the "0" level must be input to the reset pin until oscillation is stabilized.
18/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 4.3 hardware power-down mode in the msm80c48, msm80c49 and msm80c50, forcing the level at the v dd pin to a "0" during either external rom or internal rom mode results in suspension of the oscillator function and subsequent floating (high impedance) of all the i/o pins except the reset , ss and xtal 1/2 pins. the cpu is thereby stopped while maintaining internal status. 4.4 cancellation of hardware power-down mode (1) use of reset pin m the clock generator is activated and the cpu started up when a "1" level is applied to the v dd pin while a "0" level is input to the reset pin. if this "0" level is kept applied to the reset pin until oscillation become stable, the cpu will be reset and will start executing from address 0. (2) use of the int pin during external interrupt enable status (i.e. following execution of en i instruction) m the clock generator is activated and the cpu started up when a "1" level is applied to the v dd pin while a "0" level is applied to the int pin. if this "0" level is maintained until the occurrence of at least 2 ale output signals, an external interrupt is generated, and execution starts from address 3. however, if the power-down mode is started during an interrupt processing routine, execution will be continued on the next instruction after the present instruction. (3) use of the int pin during external interrupt disable mode (i.e. following excution of dis i instruction or hardware reset) m the clock generator is activated and the cpu started up when a "1" level is applied to the v dd pin while a "0" level is applied to the int pin. if this "0" level is maintained until the occurrence of at least 2 ale output signals, execution is continued on the next instruction after the present instruction. (4) use of v dd pin only m the clock generator is activated and the cpu started up when a "1" level is applied to the v dd pin while a "1" level is also applied to both the reset and int pins. in this case, execution is resumed from the stopped position.
19/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
20/20 ? semiconductor msm80c48/49/50, msm80c35/39/40 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish

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